ITSW 2006 - Call for Participation

CALL FOR PARTICIPATION

Scope -- Workshop At A Glance -- Registration & Hotel -- Committees & Contact Information

Scope

Theme: Living with Imperfection

Growing density has increased the uncertainty of the manufacturing process to the point that it is very difficult to know IC characteristics prior to manufacture. Additional uncertainty is introduced by soft and hard errors accumulated during the lifetime of the IC. Uncertainty can manifest itself directly on the functionality of the chip (i.e. stuck-at, bridging, coupling faults, and etc.) or it can have more subtle impact device parameters such as path delay, clock skew, and leakage. Testing becomes more critical in this context as a tool to characterize parts in terms of their level of functionality. In order to maintain high yield and durability in the field, defects and variations must be tolerated. Test synthesis, the consideration of test during the synthesis process, is essential to satisfy these strict requirements with low impact on design cost. The workshop will consider all aspects of test and test synthesis including, but not limited, to the following topics:

Register Transfer Level DFT
High-Level/Behavioral Test Synthesis
System-on-a-Chip (SOC) DFT
Memory and Logic BIST
Test Synthesis for Debug and Diagnosis
DFT for Mixed-Signal Circuits
Test Resource Partitioning
Functional Verification

Power and Noise-Aware Test
DFT for At-Speed Test
High-speed I/O test
Reducing the Cost of Test
Design for Manufacturing and Yield
Board and System Test
SER / Concurrent error detection
Test Synthesis for Reconfigurable Logic

Workshop At A Glance

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Monday -- Tuesday -- Wednesday

April 10, 2006 (Monday)

7:00 - 8:00 AM CONTINENTAL BREAKFAST: MEETING ROOM FOYER

8:00 - 10:00 AM Opening Session
8:00 - 8:15	Opening Message Ian Harris, General Chair
	*Keynote Addresses*
8:15 - 9:05	“On the Need to Test for Systematic Failures” Rajesh Galivanche, Intel Corporation
9:10 - 10:00	"Design for Test in the Era of Increasing Uncertainty” Janusz Rajski, Mentor Graphics Corporation

10:00 - 10:30 AM COFFEE BREAK

10:30 - 12:00 PM	Delay Test Chair: TBD
10:30 - 11:00	Timing Information for Test R. Kapur (Synopsys)
11:00 - 11:30	Dynamic Voltage Scale Aware Delay fault Testing N.B. Zain Ali and M. Zwolinski (Univ. Of Southampton)
11:30 - 12:00	Generating At-Speed Test Patterns in the Presence of Timing Exceptions and Constraints D. Goswami, K-H. Tsai, M. Kassab, and J. Rajski (Mentor Graphics)

12:00 - 1:30 PM LUNCH

1:30 - 3:30 PM	DFT Chair: TBD
1:30 - 2:00	IBM 65nm Design-for-Test Automation Solution Using Industry Standard Tools J. Pratt, D. Litten, and D. Lackey (IBM)
2:00 - 2:30	Test Set Analysis for Maximization of the Time to Failure for Test Escapes J. Dworak (Brown Univ.)
2:30 - 3:00	Verification and Debugging of Iddq Tests M. Laisne, T. Nguyen, S. Zuo, H. Cui, X. Pan, and C. Bai (Qualcomm)
3:00 - 3:30	Automated Synthesis of Hierarchical Test Comp Structures C. Barnhart (SiliconAid)

3:30 - 4:00 PM COFFEE BREAK

4:00 - 5:30 PM	BIST/Compression Chair: TBD
4:00 - 4:30	Using Rectangular Coding to Combine Linear and Non-Linear Test Vector Compression J. Lee, and N. Touba (Univ. of Texas, Austin)
4:30 - 5:00	Estimating Error Test During Self Test Via One’s Counting S. Shahidi, and S. Gupta (Univ. of Southern California, LA)
5:00 - 5:30	BIST Architecture Exploration in RTL R. Marlett (Atrenta), and D. Kay (Cisco)

DINNER (On Your Own)

April 11, 2006 (Tuesday)

7:00 - 8:00 AM CONTINENTAL BREAKFAST: MEETING ROOM FOYER

8:00 - 10:00 AM	Diagnosis / Yield Enhancement Chair: TBD
8:00 - 8:30	Early Silicon Yield Enhancement Using Volume Yield Diagnostics for Nanometer Technologies A. Uzzaman, V. Chickermane, (Cadence) and K. Iwasaki (Tokyo Metropolitan Univ., Japan)
8:30 - 9:00	Programmable Launch and Capture Clock Generation for Delay Diagnosis on Board H. Jun, and S. Chung (Cisco Systems)
11:30 - 12:00	Direct Fault Diagnosis Using Per-Pattern MISR Signatures W-T. Cheng, M. Sharma, L. Lai, and T. Rinderknecht (Mentor Graphics)
9:30 - 10:00	Synthesis for Yield - What are the issues? R. Aitken (ARM)

12:00 - 1:30 PM LUNCH

10:30-12:00PM	Memory Test and Low Power Scan Chair: TBD
10:30 - 11:00	Flash Memory Built-in Timing Test using a Sample Classification Method Y-C. Dawn, J-C. Yeh, and C-W. Wu (National Tsing Hua Univ., Taiwan)
11:00 - 11:30	A Built-in Redundancy-Analysis Scheme for RAMs with Two-Level Redundancy Y-J. Huang and J-F. Li (National Central University, Taiwan)
11:30 - 12:00	Low Power Scan Using DDR Scan Chain Design S. Bhatia (Cadence)

12:00 - 2:00 PM LUNCH ON THE BEACH (OPPOSITE DOUBLETREE HOTEL)

2:00 - 4:00 PM	Delay Test Chair: TBD
2:00 - 2:30	Function Based Test Pattern Generation for Path Delay Faults Using the Launch-of Capture Scan Architecture E. Flanigan, R. Adapa, H. Cui, M. Laisne, T. Petrov, S. Tragoudas (Southern Illinois Univ., Qualcomm)
2:30 - 3:00	Enhancing Delay Fault Coverage Through Low Power Segmented Scan Z. Zhang, S.M. Reddy, I. Pomeranz, J. Rajski, and B.M. Al-Hashimi (Univ. of Iowa, Purdue Univ., Mentor Graphics, Univ. of Southampton)
3:00 - 3:30	A Statistical Perspective on Test Set Optimization for Screening Delay Defects B. Lee, and L-C.Wang (Univ. of California, SB)
3:30 - 4:00	Power Supply Noise in Delay Testing J. Wang, D.M.H. Walker, A. Majhi, B. Kruseman, G. Gronthoud, and S. Eichenberger (Texas A&M, Philips)

4:00 - 4:30 PM COFFEE BREAK

4:30 - 6:00 PM	PANEL: Are we Fighting a Losing Battle? - Dealing with Numerous and Complex Defects Moderator: Rob Aitken (ARM)
	Panelists: Mel Breuer (Univ. of Southern California) Al Crouch (Inovys) Tom Williams (Synopsys) Sunil Khatri (Texas A&M)

6:30 - 8:30 PM SOCIAL EVENT AND DINNER
6:30 - 7:00	Cash Bar
7:00 - 8:30	Dinner and Live Entertainment

April 12, 2006 (Wednesday)

7:00 - 8:00 AM CONTINENTAL BREAKFAST: MEETING ROOM FOYER

8:00 - 10:00 AM	System Test Chair: TBD
8:00 - 8:30	A Hybrid SoC Test Model with Reconfigurable Wireless Routing D. Zao, and Y. Wang (Univ. of Louisiana)
8:30 - 9:00	Standardized Access to Embedded Test and Debug Instruments, IEEE P1687 - the Next Step M. Laisne (Qualcomm), B. Eklow (Cisco), J. Rearick (Agilent), K. Posse, A. Crouch (Inovys), J. Doege (DA-Test), B. Bennetts, and M. Ricchetti (ATI)
9:00 - 9:50	Embedded Tutorial: A Perspective on Reducing ASIC No Trouble Found (NTFs) at the System House B. Eklow, Z. Conroy, and D. Kay (Cisco)

9:50 - 10:15 AM COFFEE BREAK

10:15 - 11:45 PM	Advanced DFT Chair: TBD
10:15 - 10:45	A Unified Method for Detecting Stuck-Open Fault and Transition Faults N. Devtaprasanna, A. Gunda, P. Krishnamurthy, S.M. Reddy, and I. Pomeranz (Univ. Of Iowa, LSI Logic)
10:45 - 11:15	Comparing Gate-Exhaustive and Region-Exhaustive Testing A. Jas, S. Patil, and S. Natarajan (Intel)
11:15 - 11:45	A Highly Testable Pass Transistor based Design Methodology S. Khatri (Texas A&M)

12:00 PM ADJOURN

Registration & Hotel (Deadlines are March 27 and March 24, respectively)

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Detailed information is available at the conference web-site - http://www.tttc-itsw.org

Committees & Contact Information

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STEERING COMMITTEE

General Chair

Ian G. Harris, General Chair
Department of Computer Science
University of California Irvine
Irvine, CA 92617 U.S.A.
Email: harris@ics.uci.edu
(ph) 949-824-8842, (fax) 949-824-4056

Program Chair

Nilanjan Mukherjee, Program Chair
Design Verification and Test Division
Mentor Graphics Corporation
Willsonville, OR 97070 U.S.A.
Email: nilanjan_mukherjee@mentor.org
(ph) 503-685-1721, (fax)503-685-4729

Panels Chair

J. Dworak - Brown U.

Publicity Chair

D. Kay - Cisco Systems

Finance Chair

L. C. Wang - UC SB

Local Arrangements Chair

C. Barnhart - Cadence

European Liaison

M. Zwolinski - U. Southampton

Asian Liaison

C. W. Wu - Nat. Tsing Hua U.

Program Committee

M. Abadir - Motorola
R. Aitken - Artisan
S. Blanton - Carnegie Mellon U.
D. Burek - Magma
K. Chakrabarty - Duke U.
K.-T.Cheng - UC SB
A. Crouch - Inovys
W.-T Cheng - Mentor Graphics
S. Davidson - Sun Microsystems
J. Dworak - Brown U.
M. Hsiao - Virginia Tech.
A. Jas - Intel
R. Kapur - Synopsys
M. Laisne - QualComm
K.-J. Lee - National Cheng-Kung U.
A. Majumdar - Sun Microsystems
M. R. Mercer - Texas A&M U.
S. Mitra - Intel
K. Mohanram - Rice U. Texas
C. Papachristou - Case Western U.
J. H. Patel - U. Illinois
D. K. Pradhan - Bristol
Z. Peng - Linkoping U.
S. Oostdijk - Philips
A. Orailoglu - UC San Diego
S. Ozev - Duke U.
J. Rajski - Mentor Graphics
S. M. Reddy - U. Iowa
M. Sonza Reorda - Poli di Torino
M. Tahoori - Northeastern U.
N. Touba - U. Texas, Austin
S. Tragoudas - S. Illinois U.

For more information, visit us on the web at: http://www.tttc-itsw.org

The 13th International Test Synthesis Workshop (ITSW 2006) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).

TTTC's Electronic Broadcasting Service
	13th International Test Synthesis Workshop (ITSW 2006) April 9-12, 2006 Fess Parker's Double Tree Resort Santa Barbara, California, USA http://www.tttc-itsw.org